1. Field of the Invention
The present invention relates in general to a bootstrap circuit for boosting a voltage of an input signal, and more particularly to a bootstrap circuit for enhancing a response speed with respect to the input signal to minimize a noise effect,
2. Description of the Prior Art
Generally, a bootstrap circuit is adapted to boost a voltage of an input signal above a supply voltage to allow a circuit at a subsequent stage to generate an output signal of a sufficiently high voltage. The bootstrap circuit is provided at the front stage of a wordline driver or a data output buffer for a semiconductor integrated circuit device including an NMOS transistor, to boost the voltage of a signal being supplied to the wordline-driver or the data output buffer.
However, such a conventional bootstrap circuit has a disadvantage in that it cannot supply a sufficiently boosted voltage to the wordline driver or the data output buffer because it has a low response speed with respect to the input signal. This problem becomes more serious when an impulse noise component is contained in the input signal. For this season, the wordline driver or the data output buffer is unable to generate a normal output signal and, furthermore, the semiconductor integrated circuit device is degraded in reliability. The above-mentioned problem with the conventional bootstrap circuit will hereinafter be described in detail with reference to FIG. 1.
Referring to FIG. 1, there is shown a circuit diagram of a data output buffer fox a semiconductor integrated circuit device in which a conventional bootstrap circuit 10 is included. As shown in this drawing, the bootstrap circuit 10 is connected between a first node N1 and a second node N2. The data output buffer comprises a first NAND gate GN1 fox inputting a data signal KD from an input line 11 and an output enable signal OE from a control line When the output enable signal OE from the control line 13 is high in logic high, the first NAND gate GN1 inverts the data signal RD from the input line 11 and supplies the inverted data signal to the first node N1.
The data output buffer further comprises a first NMOS transistor MN1 having a gate for inputting a signal from the second node N2. When the signal from the second node N2 is high in level, the first NMOS transistor MN1 is turned on to generate high level data Dout on an output line 15. The high level data Dout on the output line 15 has a voltage lower than that at the second node N2 by the threshold voltage of the first NMOS transistor MN1.
The data output buffer further comprises a second NAND gate GN2, a second NMOS transistor MN2 and first and second inverters GI1 and GI2. When the output enable signal OE from the control line 13 is a logic high, the second NAND gate GN2 and the first and second inverters GI1 and GI2 invert the data signal RD from the input line 11 and supply the inverted data signal to a gate of the second NMOS transistor MN2. When the inverted data signal from the second inverter GI2 is a logic high, the second NMOS transistor MN2 is turned on, thereby causing low level (i.e., ground voltage Vss) data Dout to be generated on the output line 15.
On the other hand, the bootstrap circuit 10 includes a third inverter GI3 and a capacitor C1 connected in series between the first node N1 and a third node N3, and a third NMOS transistor MN3 connected between a supply voltage source and the third node N3 The third NMOS transistor MN3 includes a gate and a drain connected in common to the supply voltage source. When a voltage at the third node N3 is lower than a level of (supply voltage Vcc--threshold voltage of third NMOS transistor MN3), the third NMOS transistor MN3 is turned on to transfer the Supply voltage Vcc from the supply voltage source to the third node N3. The third inverter GI3 is adapted to re-invert the inverted data signal at the first node N1 and supply the re-inverted data signal to the capacitor C1. When an output signal from the third inverter GI3 is a logic low, the capacitor C1 stores the supply voltage Vcc from the supply voltage source which is transferred thereto through the third NMOS transistor MN3 and the third node N3. At this time, the voltage at the third node N3 is boosted to the level of (supply voltage Vcc--threshold voltage of third NMOS transistor MN3) according to a charge amount stored in the capacitor C1. On the contrary, when the output signal from the third inverter GI3 is a logic high, namely, it has the supply voltage Vcc, the voltage at the third node N3 is boosted to a level of (double supply voltage Vcc--threshold voltage of third NMOS transistor MN3). This results from a voltage on the capacitor C1 being added to an output voltage of the third inverter GI3.
The bootstrap circuit 10 further includes a PMOS transistor MP1 connected between the third and second nodes N3 and N2, and a fourth NMOS transistor MN4 connected between the second node N2 and a ground voltage source. The PMOS transistor MP1 and the fourth NMOS transistor MN4 have gates for inputting the data signal from the first node N1, respectively. When the data signal from the first node N1 is a logic low, the PMOS transistor MP1 is turned on to transfer the boosted voltage from the third node N3 to the Ware of the first NMOS transistor MN1 connected to the second node N2. As the PMOS transistor MP1 is turned on, the voltage charged on the capacitor C1 is discharged to the gate of the first NMOS transistor MN1 through the third node N3, the PMOS transistor MP1 and the second node N2. On the contrary, when the data signal from the first node N1 is a logic high, the fourth NMOS transistor MN4 is turned on to transfer the ground voltage Vss from the ground voltage source to the gate of the first NMOS transistor MN1 connected to the second node N2.
As mentioned above, the conventional bootstrap circuit 10 is adapted to boost the voltage of the input signal using the capacitor C1. A level of the boosted voltage is determined according to a capacitance of the capacitor C1. For this reason, the capacitor C1 must have a large capacitance to boost the voltage of the input signal to a sufficiently high level.
However, in the case where the capacitor C1 has the large capacitance, a charging time thereof becomes long, thereby causing the conventional bootstrap circuit 10 to have a low response speed with respect to the input signal. For this reason, when an impulse noise component is contained in the input signal, the conventional bootstrap circuit 10 cannot boost the voltage of the input signal to a sufficiently high level. Because of such a boosted voltage signal from the conventional bootstrap circuit 10, the pull-up NMOS transistor MN1 is unable to output the data normally and the semiconductor integrated circuit device is degraded in reliability.